Precharge type circuits are widely used in digital systems, such as dynamic logic circuits, shift registers, analog-to-digital converters, etc., to speed up the operation. In a precharge type logic circuit, there are two phases of operation. In the first phase, the load device of a driver is turned on by a clock pulse, which charges up the output node of the driver. In the second phase, a binary signal is applied to the driver to turn on or cut off the driver. If the driver is turned on, the precharged node is discharged and pulled down. Since the discharging (or pulling-down) time through the on resistance of the driver is usually shorter than the charging up (or pulling-up) time of the output node through a static load resistance, such a precharge type circuit is widely used to speed up the operation of many digital systems.
Bit line sense circuits are mainly used in the encoder and the output buffer of many analog-to-digital (A/D) converters to obtain accurate control of the timing and to speed up the output. In conventional A/D circuits, the digital data from the comparators are decoded and then encoded into binary or gray codes. However, when the encoders are of the precharge type, the digital code may arrive at the output buffer too soon or too late. If too soon, the output may produce false peaks. If too late, the conversion speed may be slowed down. In either case, the invalid time of the A/D converter output is adversely increased. In traditional A/D converters, the flash type is the fastest. Due to the limitations of resolution, power dissipation, chip size, etc., the present-day design can only achieve about 8 bits. FIG. 1 shows the simplified organization of a conventional A/D converter. The structure basically contains a voltage divider with 2.sup.M sections of resistors to produce reference voltages for 2.sup.M -1 or 2.sup.M comparators. One input terminal of each comparator is connected to a reference voltage and another input terminal is connected to the analog input signal. The comparators produce a thermometer code. The thermometer code is decoded into X-code for application to an encoder or ROM. The encoder then produce the desired y-bits of binary code or gray code. The code is delivered to the output through an output buffer.
When CMOS technology is used to implement A/D conversion, auto-zero type comparators and three-input decoders are customarily used to change the thermometer code into a logic "1" level at only one of the X-code. The outputs from the decoder are fed to the row or word lines of a following encoder. The encoder is organized in the form of a ROM. The block diagram is shown in FIG. 2. The encoder section is placed after the decoder. The column or bit lines of the encoder are connected to the drains of a number of parallel MOS transistors, individually controlled by the different word lines.
Traditionally, there are two kinds of encoders:
(1) Ratio Logic type coding:--The advantages of this type of circuit lies in its simplicity. However, since this type of logic is a static one, the power dissipation is high and the speed is slow. Furthermore, since this type is a ratio logic, the threshold voltage, hence the process, is critical.
(2) Precharge type coding:--The bit line of this type of encoder is a dynamic logic device. During the comparing time of the comparator, the bit lines of the encoder are precharged to either a high voltage or a low voltage. During the auto-zero time of the comparator to correct any mismatch of the input differential transistors, the charge on the bit lines which a particular word line controls is discharged by the only logic "1" signal from the decoder. However, the timing control of this type of encoder is very sensitive in that false peaking may appear at the output and the invalid time may increase.
FIG. 3 shows a typical precharge type circuit between the encoder and the output buffer of a conventional ADC. 110 is the precharge device for precharging the bit line 15 and controlled by a clock CK3 at input 16. The bit line 15 is connected to 2.sup.M-1 MOS transistors (MOSFET). Since only one word line has a logic "1" signal appearing at line 14, all the rest of the MOSFETs with their gates connected to other word lines are at a "0" logic level or ground, as represented by the grounded gate MOSFET symbol 112. The signal at node 15 are then transmitted through a NAND gate to the output buffer 10. The NAND gate has two p-channel MOSFETs connected in series with two n-channel MOSFETs. The signal form the precharged node is fed through an inverter to the common gate of one pair of complementary gates. The other gate 20 of the p-channel MOSFET 115 and the gate 21 of the n-channel MOSFET 114 are clocked to turn on MOSFETs 114, 115 when the clock signal CK3 is off. Then, the precharged signal appears at the output 19 of the NAND gate.
The output buffer is a latch with a complementary MOSFET transmission gate with n-channel MOSFET 117 and p-channel MOSFET 118 connecting the output 25 back to the input 19. MOSFETs 117 and 118 are also controlled by the signals at 20 and 21 to latch the output signal 25 after the clock signal CK3 is off.
Such a conventional organization has experienced problems in operation. The situation is as follows: During the comparing period of the comparator, MOSFETs 115, 114 are off, input 16 is low to turn the p-channel MOSFET 110 on and to charge the bit line 15 high. Latch 10 is latched to previous data. Next, during the auto-zero period of the comparators, both MOSFETs 114, 115 are on. When bit line 15 data "0" is to be transferred to the output buffer, error peak signals may appear. Consider the following situations:
(1) Word line 14 is low, output node 25 is initially low: Since node 15 is high and causes the output 25 to be high, there is no change in the output, and hence no error peaking signal at the output.
(2) When node 14 is low and node 25 is initially low: Since node 15 is initially high and the word line node 14 remains low, node 15 stays high. When MOSFETs 115, 114 are turned on, the output 25 changes from low to high and is stable without any error peaking signal.
(3) When node 14 is high, and node 25 is initially high: Since node 15 is initially high, the output continues to be high when MOSFETs 114 and 115 are on. Only when bit line 15 is pulled down by the high signal at node 14, then output 25 becomes low. Thus, the output 25 changes from high to low, and is stable without any error peaking.
(4) When node 14 is high and node 25 is initially low: When node 14 is high, the precharged node 15 is pulled from high to low. This pull-down action may take considerable amount of time to complete. If before node 15 becomes low, the MOSFETs 114, 115 are turned on, the output 25 may become high before falling back to low. Thus, an error peaking signal appears at the output.
The output waveform of this last situation is shown in FIG. 4. In this figure, V15 indicates the voltage at node 15. V25 indicates the voltage at node 25. Do is the output waveform of the output buffer.